Nanoscale CMOS

Above figure shows how the semiconductor device paradigm changes in nanoelectronics, which do not mean just scaling down of device dimension from micrometer to nanotemer scale but mean totally different paradigm. The scaling limits of CMOS technology (3D structure) required novel structures (2D, 1D, and 0D) and its totally different operation principle in order to obtain better performance with cost effectively. All research subject in NEEDs lab start from nanoelectronic devices.