Neuromorphic

CPU vs. Brain

Today, the efficiency of digital computing system has been dominated by complementary metal-oxide- semiconductor (CMOS) devices. For higher bit density and better performance, the dimension of CMOS has been rapidly scaled down following Moor’s law, however, off-leakage current by quantum tunneling effect constraints the increase of bit density owing to power density limits. Besides the physical limits, the conventional computing paradigm based on binary logic and Von Neumann architecture becomes increasingly inefficient as the complexity of computation increase carrying bottleneck problem. Therefore, completely new computational paradigms and architectures are required in order to extend the capability of information.
The brain of biological creatures, especially human, has superior efficiency based on ultra-high density of neuron (~1011) and its synaptic interconnection (~1015). The highly complex interconnection scheme among the neuron offer massive parallel and flexible computation with ultra-low energy consumption. In our research group, novel ultra-high density and ultra-low power neuromorphic device and circuits are studied based on nanoelectronic device with nonlinear negative differential resistance (NRD). As applications of neuromorhic architecture, short term memory (STM) and inference fields are progressed based on one to one confrontation of neuron= transistor (NDR) and synapse= memory.

Sunhae Shin, Esan Jang, Jae Won Jung


5-state Memory

Standard Ternary Inverter

The digital systems create added values by increasing bit density for better performance in complex data with cost effectively. The conventionally two-valued Boolean logic has fundamental limitation for the revolutionary increase bit density in that the number of bit cannot be larger than the number of gate. For the breakthrough of bit density limits, multi-valued logic (MVL) and memory (MVM) functions having more than one bit on single gate/wire are considered novel paradigm with strength on compact design and low power dissipation.
In our research group, novel MVM and MVL are studied based on nanoelectronic device. In order to increase bit density per unit memory circuits, the multiple negative differential resistance (NDR) is proposed based on CMOS structure. By using nonmonotonic behavior of NDR device, 5-state memory is demonstrated. In addition, novel standard ternary inverter is suggested based on conventional binary inverter circuit, which required only n*log32 bit to represent n-bit binary logic.

Sunhae Shin, Esan Jang, Jae Won Jung